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dtm modem for adsl, compatible with the following standards: ansi t1.413 issue 2 itu-t g.992.1 (g.dmt) itu-t g.992.2 (g.lite) same chip for both atu-c and atu-r supports either atm (utopia level 1 & 2) or bit- stream interface 16 bit multiplexed microprocessor interface (lit- tle and big endian compatibility) analog front end management dual latency paths: fast and interleaved atm's phy layer: cell processing (cell deline- ation, cell insertion, hec) adsl's overhead management reed solomon encode/decode trellis encode/decode (viterbi) dmt mapping/ demapping over 256 carriers fine (2ppm) timing recover using rotor and adaptative frequency domain equalizing time domain equalization front end digital filters 0.35 m m hcmos6 technology 144 pin pqfp package power consumption 1 watt at 3.3v applications atu-c: dslam, routers at central office atu-r: routers at soho, stand-alone mo- dems, pc mother boards general description the STLC60135 is the dmt modem and atm framer of the stmicroelectronics tosca ? chipset. when coupled with stlc60134 analog front-end and an external controller running dedicated firm- ware, the product fulfils ansi t1.413 aissue 2o dmt adsl specification. the STLC60135 may be used at both ends of adsl loop: atu-c and atu-r. the chip sup- ports utopia level 1 and utopia level 2 inter- face and a non atm synchronous bit-stream in- terface. september 1999 ? pqfp144 ordering number: STLC60135 STLC60135 tosca ? adsl dmt transceiver test module data symbol timing unit vcxo dsp front-end fft/ifft rotor trellis coding mapper/ demapper generic tc reed/ solomon atm specific tc interface module controller interface afe control interface test signals clock stm utopia afe interface d98tl315 afe control controller bus general purpose i/os figure 1. block diagram 1/25
absolute maximum ratings symbol parameter min typ max unit v dd supply voltage 3.0 3.3 3.6 v p tot total power dissipation 900 1400 mw t amb ambient temperature 1m/s airflow -40 85 c the STLC60135 can be splitted up into two differ- ent sections. the physical one performs the dmt modulation, demodulation, reed-solomon encod- ing, bit interleaving and 4d trellis coding. the atm section embodies framing functions for the generic and atm transmission convergence (tc) layers. the generic tc consists of data scrambling and reed solomon error corrections, with and without interleaving. the STLC60135 is controlled and programmed by an external controller (adsl transceiver con- troller, atc) that sets the programmable coeffi- cients. the firmware controls the initialization phase and carries out the consequent adaptationoperations. transient energy capabilities esd esd (electronic discharged) tests have been performed for the human body model (hbm) and for the charged device model (cdm). the pins of the device are to be able to withstand minimum 1500v for the hbm and minimum 250v for cdm. latch-up the maximum sink or source current from any pin is limited to 100ma to prevent latch-up. 1 2 3 5 6 4 7 8 9 10 46 11 47 48 49 50 51 135134133132 130 131 129128127126125 100 99 98 96 95 97 105 104 103 101 102 ad_3 vdd ad_2 ad_0 vss ad_1 vdd ad_6 ad_5 ad_4 vss u_rxdata_3 vdd u_rxdata_4 u_rxdata_5 u_rxdata_6 vss u_rxdata_7 vdd u_rx_addr_0 u_rx_addr_1 u_rx_addr_2 aftxd_0 iddq vdd aftxed_3 vss aftxed_2 aftxed_1 aftxed_0 vdd ctrldata mclk slt_dat_f1 vss slt_frame_f slr_val_f slr_dat_f0 slap_clock vdd slt_req_f slt_dat_s0 slt_dat_f0 slt_dat_s1 d98tl367b 41 42 43 44 45 136 aftxd_1 138 vss 139 aftxd_2 140 aftxd_3 141 vdd vdd u_rxdata_0 u_rxdata_1 vss u_rxdata_2 37 38 39 40 94 93 91 90 92 slr_dat_f1 slr_val_s slr_dat_s0 slr_dat_s1 vdd 12 13 14 15 16 ad_10 vss ad_9 ad_7 ad_8 54 55 56 57 58 59 124 122 123 121120119118117 u_rx_addr_3 u_rx_addr_4 vss gp_in0 vdd gp_in1 vss u_tx_refb clwd afrxd_3 vss afrxd_2 afrxd_1 afrxd_0 vdd pdown 52 53 17 18 19 88 87 89 ad_12 vdd ad_11 vss slr_frame_f slr_frame_s 86 85 83 82 84 u_tx_addr_0 u_tx_addr_1 vdd u_tx_addr_3 u_tx_addr_2 20 21 22 23 24 ad_14 ad_13 vdd vss pclk 25 26 27 80 79 81 be1 vss ad_15 u_tx_data_0 u_tx_data_1 u_tx_addr_4 78 77 75 74 76 vdd u_tx_data_2 u_tx_data_4 u_tx_data_5 u_tx_data_3 28 29 30 31 32 rdyb wr_rdb csb ale vdd 62 63 64 65 66 67 116 114 115 113112111110109 u_rx_refb u_rxclk vdd u_rxsoc u_rxclav u_rxenbb vss u_txclk gp_out trstb testse vss tck vdd tms tdo 60 61 73 u_tx_data_6 u_tx_data_7 vdd 33 34 35 resetb intb obc_type 68 69 70 u_txsoc u_tx_clav u_txenbb tdi slt_frame_s slt_req_s 36 vss vss 71 vdd 72 vss 106 107 108 137 142 143 144 figure 2. pin connection STLC60135 2/25
pin functions pin name type supply driver bs function 1 vss 0v ground 2 ad_0 b vdd bd8scr b data 0 3 ad_1 b vdd bd8scr b data 1 4 ad_2 b vdd bd8scr b address / data 2 5 vdd (v ss + 3.3v) power supply 6 ad_3 b vdd bd8scr b address / data 3 7 ad_4 b vdd bd8scr b address / data 4 8 vss 0v ground 9 ad_5 b vdd bd8scr b address / data 5 10 ad_6 b vdd bd8scr b address / data 6 11 vdd (v ss + 3.3v) power supply 12 ad_7 b vdd bd8scr b address / data 7 13 ad_8 b vdd bd8scr b address / data 8 14 ad_9 b vdd bd8scr b address / data 9 15 vss 0v ground 16 ad_10 b vdd bd8scr b address / data 10 17 ad_11 b vdd bd8scr b address / data 11 18 vdd (v ss + 3.3v) power supply 19 ad_12 b vdd bd8scr b address / data 12 20 vss 0v ground 21 pclk i vdd ibuf i processor clock 22 vdd (v ss + 3.3v) power supply 23 ad_13 b vdd bd8scr b address / data 13 24 ad_14 b vdd bd8scr b address / data 14 25 ad_15 b vdd bd8scr b address / data 15 26 vss 0v ground 27 be1 i vdd ibuf i address 1 28 ale i vdd ibuf c address latch 29 vdd (v ss + 3.3v) power supply 30 csb i vdd ibuf i chip select 31 wr_rdb i vdd ibuf i specifies the direction of the access cycle 32 rdyb oz vdd bt4cr o controls the atc bus cycle termination 33 obc_type i-pd vdd ibuf i atc mode selection (0 = i960; 1 = generic) 34 intb o vdd ibuf o requests atc interrupt service 35 resetb i vdd ibuf i hard reset 36 vss 0v ground 37 vdd (v ss + 3.3v) power supply 38 u_rxdata_0 oz vdd bd8src b utopia rx data 0 39 u_rxdata_1 oz vdd bd8src b utopia rx data 1 40 vss 0v ground 41 u_rxdata_2 oz vdd bd8src b utopia rx data 2 42 u_rxdata_3 oz vdd bd8src b utopia rx data 3 43 vdd (v ss + 3.3v) power supply STLC60135 3/25
pin functions (continued) pin name type supply driver bs function 44 u_rxdata_4 oz vdd bd8src b utopia rx data 4 45 u_rxdata_5 oz vdd bd8src b utopia rx data 5 46 vss 0v ground 47 u_rxdata_6 oz vdd bd8src b utopia rx data 6 48 u_rxdata_7 oz vdd bd8src b utopia rx data 7 49 vdd (v ss + 3.3v) power supply 50 u_rxaddr_0 i vdd ibuf i utopia rx address 0 51 u_rxaddr_1 i vdd ibuf i utopia rx address 1 52 u_rxaddr_2 i vdd ibuf i utopia rx address 2 53 u_rxaddr_3 i vdd ibuf i utopia rx address 3 54 vss 0v ground 55 u_rxaddr_4 i vdd ibuf i utopia rx address 4 56 gp_in_0 i-pd vdd ibufdq i general purpose input 0 57 vdd (v ss + 3.3v) power supply 58 gp_in_1 i-pd vdd ibufdq i general purpose input 1 59 vss 0v ground 60 u_rxrefb o vdd ibuf o 8khz clock to atm device 61 u_txrefb i vdd bt4cr i 8khz clock from atm device 62 vdd (v ss + 3.3v) power supply 63 u_rx_clk i vdd ibuf utopia rx clock 64 u_rx_soc oz vdd bd8scr utopia rx start of cell 65 u_rxclav oz vdd bd8scr utopia rx cell available 66 u_rxenbb i vdd ibuf utopia rx enable 67 vss 0v ground 68 u_tx_clk i vdd ibuf utopia tx clock 69 u_tx_soc i vdd ibuf utopia tx start of cell 70 u_txclav oz vdd bd8scr utopia tx cell available 71 u_txenbb i vdd ibuf utopia tx enable 72 vdd (v ss + 3.3v) power supply 73 vss 0v ground 74 u_txdata_7 i vdd ibuf i utopia tx data 7 75 u_txdata_6 i vdd ibuf i utopia tx data 6 76 vdd (v ss + 3.3v) power supply 77 u_txdata_5 i vdd ibuf i utopia tx data 5 78 u_txdata_4 i vdd ibuf i utopia tx data 4 79 u_txdata_3 i vdd ibuf i utopia tx data 3 80 u_txdata_2 i vdd ibuf i utopia tx data 2 81 vdd (v ss + 3.3v) power supply 82 u_txdata_1 i vdd ibuf i utopia tx data 1 83 u_txdata_0 i vdd ibuf i utopia tx data 0 84 u_txaddr_4 i vdd ibuf i utopia tx address 4 85 u_txaddr_3 i vdd ibuf i utopia tx address 3 86 vdd (v ss + 3.3v) power supply 87 u_txaddr_2 i vdd ibuf i utopia tx address 2 88 u_txaddr_1 i vdd ibuf i utopia tx address 1 89 u_txaddr_0 i vdd ibuf i utopia tx address 0 90 slr_ frame_f o vdd bt4cr frame identifier fast 91 vss 0v ground STLC60135 4/25
pin functions (continued) pin name type supply driver bs function 92 slr_frame_s o vdd bt4cr receive frame identifier interleaved 93 slr_data_s_1 o vdd bt4cr receive data interleave 1 94 slr_data_s_0 o vdd bt4cr receive data interleave 0 95 vdd (v ss + 3.3v) power supply 96 slr_val_s o vdd bt4cr receive data valid indicator interleaved 97 slr_data_f_1 o vdd bt4cr receive data fast 1 98 slr_data_f_0 o vdd bt4cr receive data fast 0 99 slr_val_f o vdd bt4cr receive data valid indicator fast 100 slap_clock o vdd bt4cr clock for slap i/f 101 slt_frame_f o vdd bt4cr transmit start of frame indicator fast 102 vss 0v ground 103 slt_data_f_1 i vdd ibufdq transmit data fast 1 104 slt_data_f_0 i vdd ibufdq transmit data fast 0 105 slt_data_s_1 i vdd ibufdq transmit data interleave 1 106 slt_data_s_0 i vdd ibufdq transmit data interleave 0 107 slt_req_f o vdd bt4cr transmit byte request fast 108 vdd (v ss + 3.3v) power supply 109 vss 0v ground 110 slt_req_s o vdd bt4cr transmit byte request interleaved 111 stl_frame_s o vdd bt4cr transmit start of frame indication interleaved 112 tdi i-pu vdd ibufuq jtag i/p 113 tdo oz vdd bt4cr jtag o/p 114 tms i-pu vdd ibufuq jtag made select 115 vdd (v ss + 3.3v) power supply 116 tck i-pd vdd ibufdq jtag clock 117 vss 0v ground 118 trstb i-pd vdd ibufdq jtag reset 119 testse i vdd ibuf none enables scan test mode 120 gp_out o vdd bd8scr o general purpose output 121 pdown o vdd bt4cr o power down analog front end (reset) 122 vdd (v ss + 3.3v) power supply 123 afrxd_0 i vdd ibuf i receive data nibble 124 afrxd_1 i vdd ibuf i receive data nibble 125 afrxd_2 i vdd ibuf i receive data nibble 126 afrxd_3 i vdd ibuf i receive data nibble 127 vss 0v ground 128 clwd i vdd ibuf i start of word indication 129 mclk i vdd ibuf c master clock 130 ctrldata o vdd bt4cr o serial data transmit channel 131 vdd (v ss + 3.3v) power supply 132 aftxed_0 o vdd bt4cr o transmit echo nibble 133 aftxed_1 o vdd bt4cr o transmit echo nibble 134 vss 0v ground 135 aftxed_2 o vdd bt4cr o transmit echo nibble 136 aftxed_3 o vdd bt4cr o transmit echo nibble 137 vdd (v ss + 3.3v) power supply 138 iddq i vdd ibuf none test pin, active high STLC60135 5/25
pin functions (continued) pin name type supply driver bs function 139 aftxd_0 o vdd bt4cr o transmit data nibble 140 aftxd_1 o vdd bt4cr o transmit data nibble 141 vss 0v ground 142 aftxd_2 o vdd bt4cr o transmit data nibble 143 aftxd_3 o vdd bt4cr o transmit data nibble 144 vdd (v ss + 3.3v) power supply i/o driver function driver function bd4cr cmos bidirectional, 4ma, slew rate control bd8scr cmos bidirectional, 8ma, slew rate control, schmitt trigger ibuf cmos input ibufdq cmos input, pull down, iddq control ibufuq cmos input, pull up, iddq control pin summary mnemonic type bs type signals function power supply vdd (v ss + 3.3v) power supply vss 0v ground atc interface ale i c 1 used to latch the address of the internal register to be accessed pclk i i 1 processor clock csb i i 1 chip selected to respond to bus cycle be1 i i 1 address 1 (not multiplexed) wr_rdb i i 1 specifies the direction of the access cycle rdyb oz o 1 controls the atc bus cycle termination intb o o 1 requests atc interrupt service ad io b 16 multiplexed address/data bus obc_type i-pd i 1 select between i960 (0) or generic (1) controller interface test access part interface tdi i-pu 1 refer to section tdo oz 1 tck i-pd 1 tms i-pu 1 trstb i-pd 1 analog front end interface afrxd i i 4 receive data nibble aftxd o o 4 transmit data nibble aftxed o o 4 transmit echo nibble clwd i i 1 start of word indication pdown o o 1 power down analog front end ctrldata o o 1 serial data transmit channel mclk i c 1 master clock STLC60135 6/25
pin summary (continued) mnemonic type bs type signals function atm utopia interface u_rxdata oz b 8 receive interface data u_txdata i i 8 transmit interface data u_rxaddr i i 5 receive interface address u_txaddr i i 5 transmit interface address u_rxclav oz o 1 receive interface cell available u_txclav oz o 1 transmit interface cell available u_rxenbb i-ttl i 1 receive interface enable u_txenbb i-ttl i 1 transmit interface enable u_rxsoc oz o 1 receive interface start of cell u_txsoc i-ttl i 1 transmit interface start of cell u_rxclk i-ttl c 1 receive interface utopia clock u_txclk i-ttl c 1 transmit interface utopia clock u_rxrefb o o 1 8khz reference clock to atm device u_txrefb i-ttl i 1 8khz reference clock from atm device atm slap interface slr_val_s o 1 slr_val_f o 1 slr_data_s o 2 slr_data_f o 2 slt_req_s o 1 slt_req_f o 1 slt_data_s i 2 slt_data_f i 2 slap_clock o 1 slr_frame_i o 1 slt_frame_i o 1 slr_frame_f o 1 slt_frame_f o 1 miscellaneous gp_in i-pd i 2 general purpose input gp_out o o 1 general purpose output resetb i i i hard reset testse i none none enable scan test mode iddq i none none test pin, active high i = input, cmos levels i-pu = input with pull-up resistance, cmos levels i-pd = input with pull-down resistance, cmos levels i-ttl = input ttl levels o = push-pull output oz = push-pull output with high-impedance state io = input / tristate push-pull output bs cell = boundary-scan cell i = input cell o = output cell b = bidirectional cell c = clock STLC60135 7/25
main block description the following drawings describe the sequence of functions performed by the chip. dsp front-end the dsp front-end contains 4 parts in the re- ceive direction: the input selector, the analog front-end interface, the decimator and the time equalizer. the input selector is used internally to enable test loopbacks inside the chip. the analog front-end lnterface transfers 16-bit words, multi- plexed on 4 input/output signals. word transfer is carried out in 4 clock cycles. the decimator receive 16-bits samples at 8.8 mhz (as sent by the analog front-end chip: stlc60134) and reduces this rate to 2.2 mhz. the time equalizer (teq) module is a fir filter with programmable coefficients. its main purpose is to reduce the effect of inter-symbol interfer- ences (isi) by shortening the channel impulse re- sponse. both the decimator and teq can be bypassed. in the transmit direction, the dsp front-end in- cludes: sidelobe filtering, clipping, delay equaliza- tion and interpolation. the sidelobe filtering and delay equalization are implemented by iir filters, reducing the effect of echo in fdm systems. clip- ping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the afe. the interpolator receives data at 2.2 mhz and generates samples at a rate of 8.8 mhz. dmt modem this module is a programmable dsp unit. its in- struction set enables the basic functions of the dmt algorithm like fft, ifft, scaling, rotor and frequency equalization (feq) in compliance with ansi t1.413 specifications. in the rx path, the 512-point fft transforms the time-domain dmt symbol into a frequency do- main representation which can be further de- coded by the subsequent demapping stages. in other words, the fast fourier transform proc- ess is used to transform from time domain to fre- quency domain (receive path). on atu-c side, 128 time samples are processed. on atu-r side, 1024 time samples are processed. after the first stage time domain equalization and fft block an ici (intercarrier interference) free information stream turns out. in select afe i/f dec teq bypass to dmt modem from analog front-end d98tl372a figure 3. dsp front-end receive trellis coding decoding fft ifft feq ftg rotor mapper demapper monitor feq coefficients to/from tc to/from dsp fe d98tl316a feq update monitor indications figure 5. dmt modem (rx & tx) filtering clipping delay equalizer interpolator afe i/f out select to analog front end from dmt modem d98tl382 figure 4. dsp front-end transmit STLC60135 8/25
this stream is still affected by carrier specific channel distortion resulting in an attenuation of the signal amplitude and a rotation of the signal phase. to compensate, a frequency domain equalizer (feq) and a rotor (phase shifter) are implemented. the frequency domain equalisation performs an operation on the received vector in order to match it with the associated point in the constellation. the coefficient used to perform the equalisation are floating point, and may be up- dated by hardware or software, using a mecha- nism of active and inactive table to avoid dmt synchro problems. in the transmit path, the ifft reverses the dmt symbol from frequency domain to time domain. the ifft block is preceded by fine tune gain (ftg) and rotor stages, allowing for a compen- sation of the possible frequency mismatch be- tween the master clock frequency and the trans- mitter clock frequency (which may be locked to another reference). the inverse fast fourier transform process is used to transform from frequency domain to time domain ( transmit path). on atu-c side, 512 fre- quencies are processed, giving 1024 samples in the time domain. on atu-r side, 256 positive frequencies are processed, giving 512 samples in the time domain. the fft module is a slave dsp engine controlled by the firmware running on an external controller. it works off line and communicates with other blocks through buffers controlled by the adata symbol timing unito. the dsp executes a pro- gram stored in a ram area, which constitutes a flexible element that allows for future system en- hancements. dpll the digital pll module receives a metric for the phase error of the pilot tone. in general, the clock frequencies at the ends (transmitter and receiver) do not match exactly. the phase error is filtered and integrated by a low pass filter, yielding an es- timation of the frequency offset. various proc- esses can use this estimate to deal with the fre- quency mismatch. in particular, small accumulated phase error can be compensated in the frequency domain by a ro- tation of the received code constellation (rotor). larger errors are compensated in the time do- main by inserting or deleting clock cycles in the sample input sequence. eventually that leads to achieve less than 2ppm between the two ends. mapper/demapper, monitor, trellis coding, feq update the demapper converts the constellation points computed by the fft to a block of bits. this means to identify a point in a 2d qam constella- tion plane. the demapper supports trellis coded demodulation and provides a viterbi maximum likelihood estimator. when the trellis is active, the demapper receives an indication for the most likely constellation subset to be used. in the transmit direction, the mapper receives a bit stream from the trellis encoder and modulates the bit stream on a set of carriers (up to 256). it generate coordinates for 2n qam constellation, where n < 15 for all carriers. the mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the ifft block. the trellis encoder generates redundant bits to improve the robust- ness of the transmission, using a 4-dimensional trellis coded modulation scheme. this feature can be disabled. the monitor computes error parameters for carri- ers specified in the demapper process. those parameters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection,etc. a series of values is constantly monitored, such as signal power, pilot phase de- viations, symbol erasures generation, loss of frame,etc. generic tc layer functions these functions relate to byte oriented data streams. they are completely described in ansi t 1.4 13. additions described in the issue 2 of pmd scrambler descrambler data patx merger rs coding decoding interleaver de-interleaver to atm tc to/from demapper d98tl317a indication bits aoc eoc pmd scrambler descrambler framer deframer fast f i f i figure 6. generic tc layer functions STLC60135 9/25
this specification are also supported. the data received from the demapper may be split into two paths, one dedicated to an inter- leaved data flow the other one for a fast data flow. no external ram is needed for the inter- leaved path. the interleaving/deinterleaving is used to in- crease the error correcting capability of block codes for error bursts. after deinterleaving (if ap- plicable), the data flow enters a reed-solomon error correcting code decoder, able to correct a number of bytes containing bit errors. the de- coder also uses the information of previous re- ceiving stages that may have detected the er- rored bytes and have labelled them with an aerasureo indicationo. each time the rs decoder detects and corrects errors in a rs codeword, an rs correction event is generated. the occurrence of such events can be signalled to the management layer. after the rs decoder, the corrected byte stream is descrambled in the pmd (physical medium de- pendent) descramblers. two descramblers are used, for interleaved and non-interleaved data flows. these are defined in ansi t1.413. after descrambling, the data flows enter the de- framer that extracts and processes bytes to sup- port physical layer related functions according to ansi t1.413. the adsl frames indeed contain physical layer-related information in addition to the data passed to the higher layers. in particular, the deframer extracts the eoc (embedded op- erations channel), the aoc (adsl overhead control) and the indicators bits and passes them to the appropriate processing unit (e.g. the trans- ceiver controller). the deframer also performs a crc check (cyclic redundancy check ) on the received frame and generates events in case of error detection. event counters can be read by management processes. the outputs of the deframer are an in- terleaved and a fast data streams. these data streams can either carry atm cells or another type of traffic. in the latter case, the atm specific tc layer functional block, described here- after, is bypassed and the data stream is directly presented at the input of the interface module. atm specific tc layer functions the 2 bytes streams (fast and slow) are received from the byte-based processing unit. when atm cells are transported, this block provides basic cell functions such as cell synchronization, cell payload descrambling, idle/unassigned cell filter, cell header error correction (hec) and detection. the cell processing happens according to itu-t i.163 standard. provision is also made for ber measurements at this atm cell level. when non cell oriented byte streams are transported, the cell processing unit is not active. the interface module collects cells (from the cell-based function module) or a byte stream (from the deframer). cells are stored in fifo's (424 bytes or 8 cell wide, transmit buffers have the same size), from which they are extracted by 2 interface sub- modules, one providing a utopia level 1 interface and the other a utopia level 2 interface. byte stream are dumped on the slap (synchro- nous link access protocol) interface. only one type of interface can be enabled in a specific configuration. dmt symbol timing unit (dstu) the dstu interfaces with various modules, like dsp frontend, fft/ifft, mapper/demapper, rs , monitor and transceiver controller. it con- sists of a real time and a scheduler modules. the real time unit generate a timebase for the dmt symbols (sample counter), superframes (symbol counter) and hyper-frames (sync counter). the timebases can be modified by various control fea- tures. they are continuously fine-tuned by the dpll module. cell scrambler descrambler synchronizer to interface module from generic tc d98tl318a fast slow hec hec cell scrambler descrambler synchronizer cell insertion/ filter ber ber cell insertion/ filter figure 7. atm specific tc layer functions utopia from atm tc d98tl319a level 1 utopia level 2 utopia level 1 utopia level 2 fast atm slow atm slap slap slow byte stream fast byte stream figure 8. interface module STLC60135 10/25
the dstu schedulers execute a program, con- trolled by program opcodes and a set of vari- ables, the most important of which are real time counters. the transmit and receive sequencers are completely independent and run different pro- grams. an independent set of variables is as- signed to each of them. the sequencer programs can be updated in real time. STLC60135 interfaces overview processor interface (atc) the STLC60135 is controlled and configured by an external processor across the processor inter- face. all programmable coefficients and parame- ters are loaded through this path. the adsl initialization is also controlled by this interface two interface types are supported; a generic asynchronous interface (i.e. powerpc or any mi- croprocessor interface) and a specific i960 inter- face. the choice is made by the obc_type pin. (0 selects i960 type interface, 1 selects generic access). data and addresses are multiplexed. STLC60135 works in 16 bits data access, so ad- dress bit 0 is not used. address bit 1 is not multi- plexed with data. it has its own pin : be1 byte acces are not supported. access cycle read or write are always in 16 bits data wide, ie bit ad- dress a0 is always zero value. the interrupt re- quest pin to the processor is intb, and is an open drain output. tle STLC60135 supports both little and big en- dian. the default feature is big endian. t a d98tl324a pclk csb ale t w t w t w t w t d t r t a rdyb ad be1 wr_rdb wait addr data in add(1) atc samples data (1): the rdyb output is continuously in tri-state, except for 2 cycles figure 10. processor interface read cycle i960 mode STLC60135 afe interface to adsl line (stlc60134) processor interface (atc) reset jtag clock digital interface utopia/bitstream interface d98tl368a figure 9. STLC60135 interfaces t a d98tl325a pclk csb ale t w t w t w t w t d t r t a rdyb ad be1 wr_rdb wait addr data out add(1) STLC60135 samples data (1): the rdyb output is continuously in tri-state, except for 2 cycles figure 11. processor interface write cycle i960 mode STLC60135 11/25
the processor interface in i960 mode the i960 mode supports a synchronous bus inter- face protocol. address and data are multiplexed. the processor is bus master and the STLC60135 is bus slave. synchronous means that all signals are synchro- nous with the input clock pclk pin. the bus cycles are directly started and driven by the processor. addresses (be1, ad[2..15]) have to be present before atc asserts the ale signal. STLC60135 latches the address on the falling edge of ale signal. the rdyb output is synchronous to pclk. a bus cycle consists of an access cycle (ta), wait cycles (tw), data cycle (td) and recovery cycle (tr). processor interface pins and functional de- scription i960 mode name type function ad[0...15] i/o multiplexed address/data bus be1 i address bit 1 ale i address latch enable wr_rdb i access direction: write (1), read (0) pclk i processor clock csb i chip select rdyb oz bus cycle ready indication intb o interrupt generic interface this interface is suitable for a number of proces- sors using a multiplexed address/data bus. in this case, synchronisation of the input signals with pclk pin is not necessary. t alew d98tl327 ale ad(15-0) t avh csb wrb ready rdb t avs t ale2cs t cs2wr t wr2d t wrw t wr2cs t wdvd t dvh t mclk t cs2rdy t csre t rdy2wr figure 12. generic processor interface write timing cycle t alew d98tl328 ale ad(15-0) t avh csb rdb ready wrb t avs t ale2cs t wr2d t wrw t rd2cs t wdvd t dvh t mclk t csrs t csre t rdy2dr t ale2z t csrd figure 13. generic processor interface read timing cycle STLC60135 12/25
generic processor interface pins and func- tional description name type function ad[0..15] i/o multiplexed address / data bus ale i address latch enable rdb i read cycle indication wrb i write cycle indication csb i chip select rdyb oz bus cycle ready indication intb o interrupt digital interface atm or serial digital interface for data to the loop before modu- lation and from the loop after demodulation. this interface collects cells (from the cell based func- tion module) or a byte stream (from the deframer). cells are stored in a fifo, 2 interfaces submodules can extract data from the fifo. byte streams are dumped on the bitstream interface (with no fifo). 3 kinds of interface are allowed utopia level 1 utopia level 2 bitstream based on a proprietary exchange the interface selection is programmed by writing the utopia phy address register. only one interface can be enabled in a st60135 configuration. utopia level 1 supports only one phy device. utopia level 2 supports multi-phy devices (see utopia level 2 specifications). each buffer provides storage for 8 atm cells (both directions for fast and interleaved channel). t alew d98tl326 ale ad(15:0) t avs t avh figure 14. waveforms symbol parameters min typ max unit tr & tf rise & fall time (10% to 90%) 3 ns talew ale pulse width 12 ns tavs address valid setup time 10 ns tavh address valid hold time 10 ns tale2cs ale to csb 0 ns tale2z ale to high z state of address bus 50 ns tcs2rdy csb to rdyb asserted 60 ns tcsre access time 900 m s tcs2wr csb to wrb 0 ns twr2d wrb to data 15 ns trdy2wr rdyb to wrb 0 ns tdvs data setup time 10 ns tdvh data hold time 1/2tmclk tmclk ns twr2cs wrb to csb -10 ns tcs2rd csb to rdb 0 ns trdy2rd rdy to rdb 0 ns trd2cs rdb to csb -10 ns tmclk master clock timing generic processor interface cycle timing all ac characteristics are indicated for a 100pf capacitive load. STLC60135 13/25
the utopia level 2 supports point to multipoint configurations by introducing an addressing capa- bility and by making distinction between polling and selecting a device. utopia level 1 interface the atm forum takes the atm layer chip as a reference. it defines the direction from atm to physical layer as the transmit direction. the di- rection from physical layer to atm is the receive direction. figures 15 & 16 show the interconnec- tion between atm and phy layer devices, the optional signals are not supported and not shown. the utopia interface transfers one byte in a sin- gle clock cycle, as a result cells are transformed in 53 clock cycles. both transmit and receive are synchronized on clocks generated by the atm layer chip, and no specific relationship between receive and transmit clocks is required. in this mode, the STLC60135 can only support one data flow : either interleaved or fast . d98tl369 rxclk rxsoc rxdata rxclav x h1 h2 p44 p45 p46 p47 p48 x rxenb figure 17. timing (utopia 1 receive interface) phy receive cell receive atm phy rxref* rxclav rxenb* rxclk rxdata 8 rxsoc d98tl330 figure 15. receiveinterface phy transmit phy txref* txclav txenb* txclk txdata 8 txsoc d98tl370 cell transmit atm layer figure 16. transmit interface pin description name type meaning usage remark rxclav o receive cell available signals to the atm chip that the STLC60135 has a cell ready for transfer remains active for the entire cell transfer rxenb* i receive enable signals to the STLC60135 that the atm chip will sample and accept data during next clock cycle rxdata and rxsoc could be tri- state when rxenb* is inactive (high). active low signal rxclk i receive byte clock gives the timing signal for the transfer, generated by atm layer chip. rxdata o receive data (8bits) atm cell data, from STLC60135 chip to atm chip, byte wide. rx data [7] is the msb. rxsoc o receive start cell identifies the cell boundary on rxdata indicate to the atm layer chip that rxdata contains the first valid byte of a cell. rxref * o reference clock 8 khz clock transported over the network active low signal *active low signal STLC60135 14/25
when rxenb is asserted, the STLC60135 reads data from its internal fifo and presents it on rxdata and rxsoc on each low-to-high transi- tion of rxclk, ie the atm layer chip samples all rxdata and rxsoc on the rising edge of rxsoc on the rising edge of rxclk. pin description name type meaning usage remark txclav o transmit cell available signals to the atm chip that the physical layer chip is ready to accept a complete cell remains active for the entire cell transfer txenb* i transmit enable signals to the STLC60135 that txdata and txsoc are valid txclk i transmit byte clock gives the timing signal for the transfer, generated by atm layer chip. txdata i transmit data (8bits) atm cell data, from atm layer chip to STLC60135, byte wide. txdata [7] is the msb. txsoc i transmit start of cell identifies the cell boundary on txdata txdata contains the first valid byte of the cell. txref * i reference clock 8khz clock from the atm layer chip *active low signal the STLC60135 samples txdata and txsoc signals on the rising edge of txclk, if txenb is asserted. txclk, rxclk, ac electrical characteristics symbol parameters min max unit f clock frequency 1.5 25 mhz tc clock duty cycle 40 60 % tj clock peak to peak jitter 5 % trf clock rise fall time 4 ns l load 100 pf txdata, txsoc, ac electrical characteristics symbol parameters min max unit t5 input set-up time to txclk 10 ns t6 hold time to txclk 1 ns l load 100 pf rxdata, rxsoc, rxclav ac electrical charac- teristics symbol parameters min max unit t7 input set-up time to txclk 10 ns t8 hold time to tx clk 1 ns t9 signal going low impedance to rxclk 10 ns t10 signal going high impedance to rxclk 0ns t11 signal going low impedance to rxclk 1ns t12 signal going high impedance to rxclk 1ns l load 100 pf d98tl371 txclk txsoc txdata txclav x h1 h2 p44 p45 p46 p47 p48 x txenb figure 18. timing (utopia 1 transmit interface) STLC60135 15/25
t5,t7 d98tl331 clock signal (highz) signal (at input) t6,t8 t11 t9 t12 t10 figure 19. timing specification (utopia 1) phy receive atm receive phy transmit atm transmit atm phy rxaddr 5 rxclav 1 rxenb* rxclk rxdata 8 rxsoc rxref* txaddr 5 txclav 1 txenb* txclk txdata 8 txsoc txref* d98tl329 figure 20. signal at utopia level 2 interface digital interface utopia level 2 interface the atm forum takes the atm layer chip as a reference. it defines the direction from atm to physical layer as the transmit direction. the di- rection from physical layer to atm is the receive direction. figure 20 shows the interconnection between atm and phy layer devices, the op- tional signals are not supported and not shown. the utopia interface transfers one byte in a sin- gle clock cycle, as a result cells are transferred in 53 clock cycles. both transmit and receive interfaces are synchro- nized on clocks generated by the atm layer chip, and no specific relationship between receive and transmit clock is assumed, they must be re- garded as mutually asynchronous clocks. flow control signals are available to match the band- width constraints of the physical layer and the atm layer. the utopia level 2 supports point to multipoint configurations by introducing on ad- dressing capability and by making a distinction between polling and selecting a device: - the atm chip polls a specific physical layer chip by putting its address on the address bus when the enb* line is asserted. the addressed physical layer answers the next cycle via the clav line re- flecting its status at that time. - the atm chip selects a specific physical layer by putting its address on the address bus when the enb* line is deasserted and asserting the enb* line on the next cycle. the addressed physical layer chip will be the target or source of the next cell transfer. STLC60135 16/25
pin description utopia 2 (receive interface) name type meaning usage remark rxclav o receive cell available signals to the atm chip that the STLC60135 has a cell ready for transfer remains active for the entire cell transfer rxenb* i receive enable signals to the physical layer that the atm chip will sample and accept data during next clock cycle rxdata and rxsoc could be tri- state when rxenb* is inactive (high) rxclk i receive byte clock gives the timing signal for the transfer, generated by atm layer chip. rxdata o receive data (8 bits) atm cell data, from physical layer chip to atm chip, byte wide. rxsoc o receive start cell identifies the cell boundary on rxdata indicate to the atm layer chip that rxdata contains the first valid byte of a cell. rxaddr i receive address (5 bits) use to select the port that will be active or polled rxref * o reference clock 8khz clock transported over the network *active low signal utopia level 2 signals the physical chip sends cell data towards the atm layer chip. the atm layer chip polls the status of the fifo of the physical layer chip. the cell exchange proceeds like: a) the physical layer chip signals the availability of a cell by asserting rxclav when polled by the atm chip. b) the atm chips selects a physical layer chip, then starts the transfer by asserting rxenb*. c) if the physical layer chip has data to send, it puts them on the rxdata line the cycle after it sampled rxenb* active. it also advances the off- set in the cell. if the data transferred is the first byte of a cell, rxsoc is 1b at the time of the data transfer, 0b otherwise. d) the atm chip accepts the data when they are available. if rxsoc was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell. STLC60135 utopia level 2 mphy operation utopia level 2 mphy operation can be done by various interface schemes. the STLC60135 sup- ports only the required mode, this mode is re- ferred to as ooperation with 1 txclav and 1 rxclavo. phy device identification the STLC60135 holds 2 phy layer utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. the associated phy address is specified by the phy_addr_x fields in the utopia phy address register. beware that an incorrect address con- figuration may lead to bus conflicts. a feature is defined to disable (tri-state) all outputs of the uto- pia interface. it is enabled by the tri_state_en bit in the rx_interface control register. STLC60135 17/25
pin description utopia 2 (transmit interface) name type meaning usage remark txclav o transmit cell available signals to the atm chip that the physical layer chip is ready to accept a cell remains active for the entire cell transfer txenb* i transmit enable signals to the physical layer that txdata and txsoc are valid txclk i transmit byte clock gives the timing signal for the transfer, generated by atm layer chip. txdata i transmit data (8 bits) atm cell data, to physical layer chip to atm chip, byte wide. txsoc i transmit start of cell identifies the cell boundary on txdata txaddr i transmit address (5 bits) use to select the port that will be active or polled txref * i reference clock 8khz clock from the atm layer chip *active low signal bitstream interface the bitstream interface is a proprietary point to point interface. the STLC60135 is the bus mas- ter of the interface. the interface is synchronous, a common clock is used. slap (synchronous link access protocol) in- terface the slap interface is a point to point bitstream interface. the STLC60135 is the bus master of the interface. the interface is synchronous, a common clock (slap_clock) is used. the basic idea is illus- trated in figure 20. the slap interface dumps the data of the fast and interleaved channels on 2 separate sub inter- faces. the data flow from the slap interface must be enabled by the transceiver controller. a disabled cell interface does not dump data on its interface. receive slap interface the interface signals use 2 signal types: (refer to fig. 22) - slr_data [1:0]: data pins, a byte is transferred in 4 cycles of 2 bits. the msb are transmitted first, odd bits are asserted on slr_data [1]. - slr_val: indicates the data transfer and the byte boundary - slr_frame: indicates the start of a super- frame notice 2 slap interfaces are supported, one for the fast data flow, the other one for the inter- leaved data flow. the logic timing diagram is shown in figure 23. external component (slave) modem (master) d98tl333 slap_clock data 2 valid frame figure 22. receive path, slap interface d ck q qn source rising clock d ck q qn falling clock sink d98tl332 slap_clock figure 21. common clock data transfer STLC60135 18/25
0123 8 minimum 8 cycles stm_clock undefined undefined frame valid b7 b5 b3 b1 b6 b4 b2 b0 one byte as 4 times 2 bits slr_data(1) slr_data(0) slr_val must not repeat in a 8 clock cycle period d98tl334 figure 23. receiveslap interface timing the implementation must guarantee that all ac- tive slr_valid signals must be separated by at least 8 clock cycles. refer to figure 23. the slr_frame signals are asserted when the first pair of bits of a frame are transferred. for the fast channel a frame is de- fined as a superframe timebase. for the interleaved channel the frame is defined by a timebase period of 4 superframes. both timebases are synchronized to the data flow. transmit slap interface the transmit interface uses the following signals (refer to figure 24) - slt_req: byte request - slt_frame: start of frame indication - slt_data [1:0] data pins, a byte is transferred 2 bits at the time in 4 successive clock cycles. msb first, odd bits on slt_data [1] the logical timing diagram is shown in figure 25. the delay between request and the associated data byte is defined as 8 cycles. the slt_frame signals are asserted when the first pair of bits of a frame are transferred. for the fast channel a frame is defined as a superframe timebase. for the interleaved channel the frame is defined by a timebase period of 4 superframes. both timebases are synchronized to the data flow and guarantee that the frame indication is as- serted when the first bits of the first dmt symbol are transferred. 0891 clock undefined slt_frame slt_request b7 b5 b3 b1 b6 b4 b2 b0 one byte in 4 cycles slt_data(1) slt_data(0) repeated each superframe/ s-frame d98tl336 11 1 02 stm_clock request may be repeated after 4 cycles delay request-data equals 8 cycles undefined figure 25. transmit slap interface timing diagram external component (slave) modem (master) d98tl335 clock data 2 request frame figure 24. interface towards phy layer t per t h t i clock all inputs all outputs t s t hd t d d98tl337 figure 26. interfacetiming STLC60135 19/25
slap interface, ac electrical characteristics symbol parameter test condition min. typ. max. unit tper clock period refer to mclk ns th clock high 11 ns tl clock low 11 ns ts setup 3 ns thd hold 2 ns td data delay 20pf load 3 6 ns analog front end control interface the analog front end interface is designed to be connected to the stlc60134 analog front end component. transmit interface the 16 bit words are multiplexed on 4 aftxd output signals. as a result 4 cycles are needed to transfer 1 word. refer to table 1 for the bit/pin al- location for the 4 cycles. the first of 4 cycles is identified by the clwd signal. refer to figure 26. the STLC60135 fetches the 16 bit word to be multiplexed on aftxd from the tx digital front- end module. receive interface the 16 bit receive word is multiplexed on 4 afrxd input signals. as a result 4 cycles are needed to transfer 1 word. refer to table 2 for the bit / pin allocation for the 4 cycles. the first of 4 cycles is identified by the clwd must repeat after 4 mclk cycles. cycle0 cycle1 cycle2 cycle3 test0 test1 test2 test3 d98tl320 mclk clwd aftxd aftxed gp_out figure 27. transmittword timing diagram cycle0 cycle1 cycle2 cycle3 test0 test1 test2 test3 d98tl321 mclk clwd afrxd gp_in(0) figure 28. receiveword timing diagram table 1: transmitted bits assigned to signal / time slot cycle 0 cycle 1 cycle 2 cycle 3 aftxd[0] b0 b4 b8 b12 aftxd[1] b1 b5 b9 b13 aftxd[2] b2 b6 b10 b14 aftxd[3] b3 b7 b11 b15 gp_out t0 t1 t2 t3 table 2: transmitted bits assigned to signal / time slot cycle 0 cycle 1 cycle 2 cycle 3 afrxd[0] b0 b4 b8 b12 afrxd[1] b1 b5 b9 b13 afrxd[2] b2 b6 b10 b14 afrxd[3] b3 b7 b11 b15 gp_in t0 t1 t2 t3 tc tv d98tl322 mclk clwd aftxd aftxed figure 29. transmit interface th ts d98tl323 mclk afrxd figure 30. receive interface STLC60135 20/25
table 3: master clock (mclk) ac electrical characteristics symbol parameter test condition min. typ. max. unit f clock frequency 35.328 mhz tper clock period 28.3 ns th clock duty cycle 40 60 % table 4: aftxd, aftxed, clwd ac electrical characteristics symbol parameter test condition min. typ. max. unit tv data valid time 0 10 ns tc data valid time 0 10 ns table 5: afrxd ac electrical characteristics symbol parameter test condition min. typ. max. unit ts data setup time 5 ns th data hold time 5 ns tests, clock, jtag interface - mclk: master clock (35.328mhz) generated by vcxo - atm receive interface, asynchronous clock gen- erated by utopia master - atm transmit interface, asynchronous clock generated by utopia master - atc clock (pclk): external asynchronous clock (synchronous with atc in case of i960 specific in- terface) jtag tp interface: standard test access port, used with the boundary scan for chip and board testing. this jtag tap interface consists in 5 signals: tdi, tdo, tck & tms. tsrtb: test reset, reset the tap controller. trstb is an active low signal. table 6: boundary scan chain sequence sequence number mnemonic pin bs type 2 ad_0 b 3 ad_1 b 4 ad_2 b 6 ad_3 b 7 ad_4 b 9 ad_5 b 10 ad_6 b 12 ad_7 b 13 ad_8 b 14 ad_9 b 16 ad_10 b 17 ad_11 b 19 ad_12 b 21 pclk i 23 ad_13 b 24 ad_14 b 25 ad_15 b 27 be1 i 28 ale c 30 csb i 31 wr_rdb i 32 rdyb o 33 obc_type i 34 intb o 35 resetb i 38 u_rxdata_0 b 39 u_rxdata_1 b 41 u_rxdata_2 b 42 u_rxdata_3 b 44 u_rxdata_4 b 45 u_rxdata_5 b 46 vss 47 u_rxdata_6 b 48 u_rxdata_7 b 50 u_rxaddr_0 i 51 u_rxaddr_1 i 52 u_rxaddr_2 i 53 u_rxaddr_3 i 55 u_rxaddr_4 i 56 gp_in_0 i 58 gp_in_1 i 60 u_rxrefb o STLC60135 21/25
table 6: (continued) sequence number mnemonic pin bs type 61 u_txrefb i 63 u_rxclk 64 u_rxsoc 65 u_rxclav 66 u_rxenbb 68 u_txclk 69 u_txsoc 70 u_txclav 71 u_txenbb 74 u_txdata_7 i 75 u_txdata_6 i 77 u_txdata_5 i 78 u_txdata_4 i 79 u_txdata_3 i 80 u_txdata_2 i 82 u_txdata_1 i 83 u_txdata_0 i 84 u_txaddr_4 i 85 u_txaddr_3 i 87 u_txaddr_2 i 88 u_txaddr_1 i 89 u_txaddr_0 i 90 slr_frame_f 92 slr_frame_s 93 slr_data_s_1 94 slr_data_s_0 96 slr_data_s 97 slr_data_f_1 98 slr_data_f_0 99 slr_val_f 100 slap_clock 101 slt_frame_f 103 slt_data_f_1 104 slt_data_f_0 105 slt_data_s_1 106 slt_data_s_0 107 slt_req_f 110 slt_req_s 111 slt_frame_s 112 tdi 113 tdo 114 tms 116 tck 118 trstb 119 testse none 120 gp_out o 121 pdown o 123 afrxd_0 i 124 afrxd_1 i 125 afrxd_2 i 126 afrxd_3 i 128 clwd 1 i 129 mclk 1 c 130 ctrldata 1 o 132 aftxed_0 o 133 aftxed_0 o 135 aftxed_0 o 136 aftxed_0 o 138 iddq none 139 aftxd_0 o 140 aftxd_1 o 142 aftxd_0 o 143 aftxd_1 o general purpose i/o register 2 general purpose register (0x040) field type position bits length function gp_in r [0,1] 2 sampled level on pins gp_in gp_out rw [2] 1 output level on pins gp_out bits from 3 to 15 are reserved reset initialization the STLC60135 supports two reset modes: - a 'hardware' reset is activated by the resetb pin (active low). a hard reset occurs when a low input value is detected at the resetb input. the low level must be applied for at least 1ms to guarantee a correct reset operation. all clocks and power supplies must be stable for 200ns prior to the rising edge of the resetb signal. - 'soft' reset activated by the controller write ac- cess to a soft reset configuration bit. the reset process takes less than 10000 mclk clock cy- cles. electrical specifications generic the values presented in the following table apply for all inputs and/or outputs unless specified oth- erwise. specifically they are not influenced by the choice between cmos or ttl levels. STLC60135 22/25
dc electrical characteristics (all voltages are referenced to vss, unless otherwise specified, positive current is towards the device) io buffers generic dc characteristics symbol parameter test condition min. typ. max. unit i in input leakage current v in =v ss ,v dd no pull up / pull down -10 10 m a i oz tristate leakage current v in =v ss ,v dd no pull up / pull down -10 10 m a i pu pull up current v in =v ss -25 -66 -125 ma i pd pull down current v in =v dd 25 66 125 ma r pu pull up resistance v in =v ss 50 k w r pd pull down resistance v in =v dd 50 k w io buffers dynamic dc characteristics important for transient but measured at (near) dc symbol parameter test condition min. typ. max. unit c in input capacitance @f = 1mhz 5 pf dl/dt current derivative 8ma driver, slew rate control 23.5 ma/ns 8ma driver, no slew rate control 89 -125 ma/ns i peak peak current 8ma driver, slew rate control 85 ma 8ma driver, no slew rate control 100 ma c out output capacitance (also bidirectional and tristate drivers) @f = 1mhz 7 pf input / output cmos generic characteristics the values presented in the following table apply for all cmos inputs and/or outputs unless specified otherwise. cmos io buffers generic characteristics symbol parameter test condition min. typ. max. unit v il low level input voltage 0.2 x v dd v v ih high level input voltage 0.8 x v dd v v hy schmitt trigger hysteresis slow edge < 1v/ms, only for schmitx 0.8 v v ol low level output voltage i out = xma* 0.4 v v oh high level output voltage i out = xma* 0.85 x v dd v * the reference current is dependent on the exact buffer chosen and is a part of the buffer name. the available values are 2, 4 and 8ma. input/ output ttl generic characteristics the values presented in the following table apply for all ttl inputs and/or outputs unless specified oth- erwise symbol parameter test condition min. typ. max. unit v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v ilhy low level threshold, falling slow edge < 1v/ms 0.9 1.35 v v ihhy high level threshold, rising slow edge < 1v/ms 1.3 1.9 v v hy schmitt trigger hysteresis slow edge < 1v/ms 0.4 0.7 v v ol low level output voltage i out = xma* 0.4 v v oh high level output voltage i out = xma* 2.4 v * the reference current is dependent on the exact buffer chosen and is a part of the buffer name. the available values are 2, 4 and 8ma. STLC60135 23/25
pqfp144 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 4.07 0.160 a1 0.25 0.010 a2 3.17 3.42 3.67 0.125 0.135 0.144 b 0.22 0.38 0.009 0.015 c 0.13 0.23 0.005 0.009 d 30.95 31.20 31.45 1.219 1.228 1.238 d1 27.90 28.00 28.10 1.098 1.102 1.106 d3 22.75 0.896 e 0.65 0.026 e 30.95 31.20 31.45 1.219 1.228 1.238 e1 27.90 28.00 28.10 1.098 1.102 1.106 e3 22.75 0.896 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k 0 (min.), 7 (max.) a a2 a1 b c 36 37 72 73 108 10 9 144 e3 d3 e1 e d1 d e 1 k b pqfp14 4 l l1 sea ting plan e 0. 10mm .004 STLC60135 24/25
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics tosca ? is trademark of stmicroelectronics ? 1999 stmicroelectronics and alcatel alsthom, paris printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com STLC60135 25/25

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